A four-phase handshaking asynchronous static RAM design for self-timed systems
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AbstractThe motivation of designing asynchronous memory arises from the recent development of asynchronous processors. As different from the conventional design, the proposed asynchronous static RAM can 1) communicate with other asynchronous systems based on a four-phase handshaking control protocol and 2) generate the read/write completion signals with increased average speed by the variable bit-line load concept. The techniques investigated include 1) dual-rail voltage sensing completion detection for read operation and 2) multiple delays completion generation for write operation, In this paper, the performances of these techniques are evaluated for 1-Mb memory with four regions of bit-line segmentation. The simulated and measured results are presented and compared.
All Author(s) ListSit VWY, Choy CS, Chan CF
Journal nameIEEE Journal of Solid-State Circuits
Year1999
Month1
Day1
Volume Number34
Issue Number1
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Pages90 - 96
ISSN0018-9200
eISSN1558-173X
LanguagesEnglish-United Kingdom
Keywordsasynchronous; memory; self-timed systems
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

Last updated on 2020-14-10 at 01:33