SEU reliability evaluation of 3D ICs
Publication in refereed journal


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AbstractThe single-event-upset (SEU) reliability is a concern for three-dimensional (3D) integrated circuits (ICs), mainly due to the carrier mobility change caused by thermo-mechanical stress from through-silicon vias (TSVs) and the shallow trench isolation (STI). A systematic evaluation method is proposed to identify the vulnerability within 3D ICs at design time. The evaluation flow involves the TSV/STI stress-aware mobility variation calculation, sensitive region marking, insertion of excitation signals and then the simulation of the 3D ICs. This method is able to help 3D IC designers to evaluate and enhance the SEU reliability at design time.
All Author(s) ListLi HY, Hu XB, Shao CP, Zhou JB, Xu GQ
Journal nameElectronics Letters
Year2015
Month2
Day19
Volume Number51
Issue Number4
PublisherINST ENGINEERING TECHNOLOGY-IET
Pages362 - 363
ISSN0013-5194
eISSN1350-911X
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic

Last updated on 2020-27-11 at 01:51