InTimeFix: A Low-Cost and Scalable Technique for In-Situ Timing Error Masking in Logic Circuits
Refereed conference paper presented and published in conference proceedings


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摘要With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel in-situ timing error masking technique, namely InTimeFix, by introducing fine-grained redundant approximation circuit into the design to provide more timing slack for speed-paths. The synthesis of the redundant circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. Experimental results show that InTimeFix significantly increases circuit timing slack with low area/power cost.
著者Yuan F, Xu Q
會議名稱50th ACM/EDAC/IEEE Design Automation Conference (DAC)
會議開始日29.05.2013
會議完結日07.06.2013
會議地點Austin
會議國家/地區美國
詳細描述organized by IEEE/ACM,
出版年份2013
月份1
日期1
出版社IEEE COMPUTER SOC
電子國際標準書號978-1-4503-2071-9
國際標準期刊號0738-100X
語言英式英語
Web of Science 學科類別Computer Science; Computer Science, Theory & Methods; Engineering; Engineering, Electrical & Electronic

上次更新時間 2020-25-11 於 01:48