InTimeFix: A Low-Cost and Scalable Technique for In-Situ Timing Error Masking in Logic Circuits
Refereed conference paper presented and published in conference proceedings


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AbstractWith technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel in-situ timing error masking technique, namely InTimeFix, by introducing fine-grained redundant approximation circuit into the design to provide more timing slack for speed-paths. The synthesis of the redundant circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. Experimental results show that InTimeFix significantly increases circuit timing slack with low area/power cost.
All Author(s) ListYuan F, Xu Q
Name of Conference50th ACM/EDAC/IEEE Design Automation Conference (DAC)
Start Date of Conference29/05/2013
End Date of Conference07/06/2013
Place of ConferenceAustin
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE/ACM,
Year2013
Month1
Day1
PublisherIEEE COMPUTER SOC
eISBN978-1-4503-2071-9
ISSN0738-100X
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Theory & Methods; Engineering; Engineering, Electrical & Electronic

Last updated on 2020-10-10 at 23:41