Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
Publication in refereed journal

香港中文大學研究人員

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摘要We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated with three-dimensional (3-D) integration technology. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for test-access mechanisms. In addition, a thermal-aware test scheduling algorithm is proposed to eliminate hot spots during manufacturing test. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.
著者Jiang L, Xu Q, Chakrabarty K, Mak TM
期刊名稱IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版年份2012
月份9
日期1
卷號20
期次9
出版社IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
頁次1621 - 1633
國際標準期刊號1063-8210
電子國際標準期刊號1557-9999
語言英式英語
關鍵詞Pre-bond test; test architecture design and optimization; thermal-aware test scheduling; three-dimensional (3-D) integrated circuits (ICs); through-silicon via (TSV)
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

上次更新時間 2020-21-10 於 00:41