A 6-mu W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology
Publication in refereed journal

香港中文大學研究人員

引用次數
替代計量分析
.

其它資訊
摘要An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 mu W under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 mu s.
著者Guo JP, Leung KN
會議名稱Bipolar/BiCMOS Circuits and Technology Meeting
會議開始日12.10.2009
會議完結日14.10.2009
會議地點Capri
期刊名稱IEEE Journal of Solid-State Circuits
出版年份2010
月份9
日期1
卷號45
期次9
出版社IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
頁次1896 - 1905
國際標準期刊號0018-9200
電子國際標準期刊號1558-173X
語言英式英語
關鍵詞Capacitor-less; low-dropout regulator (LDO); nano-scale technology; transient response
Web of Science 學科類別Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

上次更新時間 2020-01-12 於 00:17