Multi-bend bus driven floorplanning
Publication in refereed journal


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其它資訊
摘要In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73] is not able to generate any solution while our algorithm can still give solutions of good quality. (C) 2007 Elsevier B.V. All rights reserved.
著者Law JHY, Young EFY
期刊名稱Integration
出版年份2008
月份2
日期1
卷號41
期次2
出版社ELSEVIER SCIENCE BV
頁次306 - 316
國際標準期刊號0167-9260
電子國際標準期刊號1872-7522
語言英式英語
關鍵詞bus-driven; CAD; floorplanning; physical design; simulated annealing
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

上次更新時間 2021-23-02 於 00:42