A multi-core debug platform for NoC-Based systems
Refereed conference paper presented and published in conference proceedings


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AbstractNetwork-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug architecture for bus-based systems is not readily applicable to identify bugs in NoC-based systems, in this paper. we present a novel debug platform that supports concurrent debug access to the cores under debug (CUDs) and the NoC in a unified architecture. By introducing core-level debug probes in between the CUDs and their network interfaces and a system-level debug agent controlled by an off-chip multi-core debug controller the proposed debug platform provides in-depth analysis features for NoC-based systems, such as NoC transaction analysis, multi-core cross-triggering and global synchronized timestamping Therefore, the proposed solution is expected to facilitate the designers to identify bugs in NoC-based systems more effectively and efficiently. Experimental results show that the design-for-debug cost for the proposed technique in terms of area and traffic requirements is moderate(1)..
All Author(s) ListTang S, Xu Q
Name of ConferenceDesign, Automation and Test in Europe Conference and Exhibition (DATE 07)
Start Date of Conference16/04/2007
End Date of Conference20/04/2007
Place of ConferenceNice
Country/Region of ConferenceFrance
Detailed descriptionorganized by IEEE/ACM,
Year2007
Month1
Day1
PublisherIEEE
Pages870 - 875
ISBN978-3-9810801-2-4
ISSN1530-1591
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesAutomation & Control Systems; Engineering; Engineering, Electrical & Electronic; Engineering, Mechanical

Last updated on 2020-28-05 at 03:37