A 75dB image rejection IF-Input quadrature sampling SC Sigma Delta modulator
Refereed conference paper presented and published in conference proceedings


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AbstractQuadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (1) and quadrature (Q) paths of analog circuitry. This paper presents an IF-input quadrature- sampling switched-capacitor (SC) Sigma Delta modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q paths the critical components, namely, the sampling capacitors and the capacitors of the first-stage feedback digital-to-analog converter. Moreover, a clocking scheme insensitive to I/Q phase imbalance is used. A 3(rd) order lowpass single-loop 1-bit modulator has been designed and fabricated in a 0.35 mu m CMOS process with 2 an active area of 0.57mm. Experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 100 kHz bandwidth.
All Author(s) ListCheng WT, Pun KP, Choy CS, Chan CF
Name of Conference31st European Solid-State Circuits Conference
Start Date of Conference12/09/2005
End Date of Conference16/09/2005
Place of ConferenceGrenoble
Country/Region of ConferenceFrance
Detailed descriptionorganized by IEEE,
Year2005
Month1
Day1
PublisherIEEE
Pages455 - 458
ISBN0-7803-9205-1
ISSN1930-8833
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic

Last updated on 2020-08-04 at 02:22