A 75dB image rejection IF-Input quadrature sampling SC Sigma Delta modulator
Refereed conference paper presented and published in conference proceedings


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摘要Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (1) and quadrature (Q) paths of analog circuitry. This paper presents an IF-input quadrature- sampling switched-capacitor (SC) Sigma Delta modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q paths the critical components, namely, the sampling capacitors and the capacitors of the first-stage feedback digital-to-analog converter. Moreover, a clocking scheme insensitive to I/Q phase imbalance is used. A 3(rd) order lowpass single-loop 1-bit modulator has been designed and fabricated in a 0.35 mu m CMOS process with 2 an active area of 0.57mm. Experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 100 kHz bandwidth.
著者Cheng WT, Pun KP, Choy CS, Chan CF
會議名稱31st European Solid-State Circuits Conference
會議開始日12.09.2005
會議完結日16.09.2005
會議地點Grenoble
會議國家/地區法國
詳細描述organized by IEEE,
出版年份2005
月份1
日期1
出版社IEEE
頁次455 - 458
國際標準書號0-7803-9205-1
國際標準期刊號1930-8833
語言英式英語
Web of Science 學科類別Engineering; Engineering, Electrical & Electronic

上次更新時間 2021-19-06 於 00:55