Embedded computation of maximum-likelihood phylogeny inference using platform FPGA
Refereed conference paper presented and published in conference proceedings

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AbstractOur previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this platform, a microprocessor is immersed into field programmable gate array (FPGA) fabric for realizing an effective environment for HW/SW co-design implementation. Significant improvements in data transmission between hardware and software and higher clock frequency of FPGA have been realized when compared to the JBits interface in the previous design. In addition, the embedded platform provides a greater flexibility in partitioning hardware and software tasks. These new features lead to much faster computation speed for phylogeny inference. In this paper, the architecture for HW/SW co-design in the embedded platform is presented The FPGA logic design for the tree likelihood evaluation has also been improved to tackle problem of larger scale by adopting the idea of partial likelihood.
All Author(s) ListMak TST, Lam KP
Name of ConferenceIEEE Computational Systems Bioinformatics Conference (CSB 2004)
Start Date of Conference16/08/2004
End Date of Conference19/08/2004
Place of ConferenceStanford
Country/Region of ConferenceUnited States of America
Year2004
Month1
Day1
PublisherIEEE COMPUTER SOC
Pages512 - 514
ISBN0-7695-2194-0
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesBiotechnology & Applied Microbiology; Computer Science; Computer Science, Artificial Intelligence; Computer Science, Interdisciplinary Applications; Genetics & Heredity

Last updated on 2020-02-08 at 02:31