Field programmable gate arrays and analog implementation of BRIN for optimization problems
Refereed conference paper presented and published in conference proceedings

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AbstractThe Binary Relation Inference Network (BRIN) emerges as a powerful topological network to solve various constrained optimization problems. In this paper, the BRIN solution is reviewed for the sake of reference. The analog and digital realization of BRIN is presented. For the analog implementation, we studied the BRIN solution for transitive closure problem. We used the common available integrated circuits and general minimum and maximum building blocks. The network response was discussed. The worst solution time for a general path problem was estimated. For digital implementation, Field Programmable Gates Arrays (FPGA) with million gates for BRIN solution was studied with Xilinx's System Generator. The detailed implementation is presented. The network response and the solution time are analyzed. The comparisons between both platforms are discussed.
All Author(s) ListNg HS, Mak ST, Lam KP
Name of ConferenceIEEE International Symposium on Circuits and Systems
Start Date of Conference25/05/2003
End Date of Conference28/05/2003
Place of ConferenceBANGKOK
Country/Region of ConferenceThailand
Year2003
Month1
Day1
PublisherIEEE
Pages73 - 76
ISBN0-7803-7761-3
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Artificial Intelligence; Computer Science, Hardware & Architecture; Engineering; Engineering, Electrical & Electronic

Last updated on 2020-03-08 at 03:35