Two-Stage Miller-Compensated Amplifier with Embedded Negative Current Buffer
Refereed conference paper presented and published in conference proceedings


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AbstractA two-stage simple Miller-compensated (SMC) amplifier with embedded negative current buffer design is presented in this paper. The compensation technique based on current buffer allows elimination of the right half-plane zero in SMC system, offers significant improvement in bandwidth and considerably lowers the compensation capacitance requirement. Simulation results show that the unity-gain frequency is extended by 22.6 times by the proposed design, while the power consumption is only increased by 28.3%. The required compensation capacitance is also decreased by 28 times.
All Author(s) ListHo M, Leung KN
Name of ConferenceIEEE International Conference of Electron Devices and Solid-State Circuits
Start Date of Conference08/12/2008
End Date of Conference10/12/2008
Place of ConferenceHong Kong
Country/Region of ConferenceChina
Detailed descriptionorganized by IEEE ED/SSC Hong Kong Joint Chapter,
Year2008
Month1
Day1
PublisherIEEE
Pages25 - 28
ISBN978-1-4244-2539-6
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic

Last updated on 2020-29-11 at 00:29