A 2.5-Mbps, 170-cm Transmission Distance IntraBody Communication Receiver Front End Design And Its Synchronization Technique Research
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員

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摘要This paper presents an IntraBody Communication (IBC) based receiver front end module design. By introducing Binary Signal Recovery (BSR) module with Blind Oversampling Clock and Data Recovery (BOCDR) synchronization technique, the proposed receiver achieves data speed-2.5Mb/s and transmission distance-170cm with 1.84e-6 Bit Error Rate (BER). In the proposed IBC receiver, distorted and noisy signal received by the IBC receiver is first processed by BSR block for coarse binary signal recovery. Then BOCDR is followed to further increase the transmission accuracy and meanwhile extract clock phase information as the transmitter and receiver work upon asynchronous clocks. To verify the proposed scheme, BSR module is implemented with discrete components. BOCDR is fully digital system and realized with FPGA. The measurement result shows its competitive performance with other similar work. The proposed IBC receiver front end scheme is successfully applied to an FPGA based audio player, which plays a significant role for technique verification and further IBC application.
著者Wang H, Wang JF, Choy CS
會議名稱57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
會議開始日03.08.2014
會議完結日06.08.2014
會議地點College Station
會議國家/地區美國
出版年份2014
月份1
日期1
出版社IEEE
頁次643 - 646
電子國際標準書號978-1-4799-4132-2
國際標準期刊號1548-3746
語言英式英語
關鍵詞audio player; binary signal recovery; bit error rate; blind oversampling clock and data recovery; FPGA; IntraBody Communication; return to zero coding
Web of Science 學科類別Computer Science; Computer Science, Information Systems; Engineering; Engineering, Electrical & Electronic

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