A 5 GHz, Integrated Transformer based, Variable Power Divider Design in CMOS Process
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員

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摘要This paper presents, for the first time, the realization of CMOS power divider with variable dividing ratio. Size reduction is attained by the adoption of lumped-LC networks based on on-chip capacitors and integrated differential transformers. The proposed design offers a tuning range of about 9dB with standard CMOS tuning diodes and low control voltage. For demonstration, both simulated and measured results of a 5GHz variable power divider implemented using 0.35 mu m CMOS process are shown.
著者Chik MCJ, Li W, Cheng KKM
會議名稱3rd Asia-Pacific Microwave Conference Proceedings (APMC)
會議開始日05.11.2013
會議完結日08.11.2013
會議地點Seoul
會議國家/地區韓國
詳細描述, Korean Institute of Electromagnetic Engineering and Science (KIEES),
出版年份2013
月份1
日期1
出版社IEEE
頁次366 - 368
電子國際標準書號978-1-4799-1472-2
語言英式英語
關鍵詞CMOS; power dividers; power dividing ratio; transformer; tunable; variable
Web of Science 學科類別Engineering; Engineering, Electrical & Electronic; Telecommunications

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