A 5 GHz, Integrated Transformer based, Variable Power Divider Design in CMOS Process
Refereed conference paper presented and published in conference proceedings


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AbstractThis paper presents, for the first time, the realization of CMOS power divider with variable dividing ratio. Size reduction is attained by the adoption of lumped-LC networks based on on-chip capacitors and integrated differential transformers. The proposed design offers a tuning range of about 9dB with standard CMOS tuning diodes and low control voltage. For demonstration, both simulated and measured results of a 5GHz variable power divider implemented using 0.35 mu m CMOS process are shown.
All Author(s) ListChik MCJ, Li W, Cheng KKM
Name of Conference3rd Asia-Pacific Microwave Conference Proceedings (APMC)
Start Date of Conference05/11/2013
End Date of Conference08/11/2013
Place of ConferenceSeoul
Country/Region of ConferenceSouth Korea
Detailed description, Korean Institute of Electromagnetic Engineering and Science (KIEES),
Year2013
Month1
Day1
PublisherIEEE
Pages366 - 368
eISBN978-1-4799-1472-2
LanguagesEnglish-United Kingdom
KeywordsCMOS; power dividers; power dividing ratio; transformer; tunable; variable
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic; Telecommunications

Last updated on 2020-08-04 at 00:53