Dynamic Programming Networks for Large-Scale 3D Chip Integration
Publication in refereed journal

Times Cited
Web of Science7WOS source URL (as at 10/08/2020) Click here for the latest count
Altmetrics Information

Other information
AbstractRecent technological advance in three-dimensional (3-D) on-chip systems integration provides a promising platform to realize multicore, multiprocessor, and networks-on-chip (NoC) based systems with augmented performance. With the additional tightly coupled physical layers, onchip system complexity grows significantly. The provision for efficient run-time management in large-scale system becomes critical. In this article, we review the design of an emerging on-chip dynamic-programming (DP) network [3] [5], of which the capabilities have been demonstrated in a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. A design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3-D) architecture using through-silicon-via (TSV) CMOS technology [1], is also presented. The vertical inter-layer communication is achieved by the means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. Testing results demonstrated the effectiveness of such approach for deadlock detection and the minuscule computational delay for detecting deadlock from a large-scale network.
All Author(s) ListMak T, Al-Dujaily R, Zhou K, Lam KP, Meng YC, Yakovlev A, Poon CS
Journal nameIEEE Circuits and Systems Magazine -New Series-
Volume Number11
Issue Number3
Pages51 - 62
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesEngineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

Last updated on 2020-11-08 at 01:51