A 0.5-V 81.2 dB SNDR audio-band continuous-time Delta-Sigma modulator with SCR feedback
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香港中文大學研究人員

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摘要This manuscript presents a 0.5-V audio-band continuous-time Delta-Sigma modulator with a new method implementing switched-capacitor-resistor (SCR) feedback to reduce clock jitter-induced noise. An ultra-low voltage (ULV) amplifier with self-compensated CMFB loop is used to meet the stricter amplifier speed required by SCR feedback. Fabricated in a 0.13 mu m CMOS process, the modulator achieves a peak SNDR of 81.2 dB over 25-kHz signal bandwidth and consumes 625 mu W at 0.5-V supply.
著者Chen Y, Pun KP, Kinget P
期刊名稱Analog Integrated Circuits and Signal Processing
出版年份2011
月份6
日期1
卷號67
期次3
出版社Springer Verlag (Germany)
頁次285 - 292
國際標準期刊號0925-1030
電子國際標準期刊號1573-1979
語言英式英語
關鍵詞Continuous-time Delta-Sigma modulator; Low-voltage amplifier; Ultra-low voltage circuits
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

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