Characterizing the Lifetime Reliability of Manycore Processors with Core-Level Redundancy
Refereed conference paper presented and published in conference proceedings


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AbstractWith aggressive technology scaling, integrated circuits suffer from ever-increasing wearout effects and their lifetime reliability has become a serious concern for the industry. For manycore processors that integrate a large number of processor cores on a single silicon die, introducing core-level redundancy is an effective way to alleviate this problem. There are, however, many strategies to make use of the redundant cores, which have different implications on the aging effects of embedded processors. How to characterize the lifetime reliability of manycore processors with different usages is therefore an important and relevant problem. In this paper, we propose a novel analytical method to tackle the above problem, which captures the impact of workloads and the associated temperature variations. We then use the proposed model to analyze the lifetime reliability for manycore processors with various redundancy configurations. Finally, the effectiveness of the proposed method is demonstrated with extensive experiments.
All Author(s) ListHuang L, Xu QA
Name of ConferenceIEEE and ACM International Conference on Computer-Aided Design
Start Date of Conference07/11/2010
End Date of Conference11/11/2010
Place of ConferenceSan Jose
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE/ACM,
Year2010
Month1
Day1
PublisherIEEE
Pages680 - 685
eISBN978-1-4244-8192-7
ISSN1933-7760
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Theory & Methods; Engineering; Engineering, Electrical & Electronic

Last updated on 2021-19-02 at 23:58