A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator
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摘要This manuscript reports a 0.5 V 1-MHz signal bandwidth third-order continuous-time complex Delta Sigma modulator for analog-to-digital conversion in GFSK receivers. A special common-mode level arrangement and gate-input self-biased amplifiers allows the modulator to meet the speed requirement at the low supply voltage. Realized in a 0.13-mu m triple-well CMOS process and using only standard V-T devices, the modulator achieves a peak SNDR of 61.9 dB, a dynamic range of 65.7 dB and an image rejection ratio of 46.3 dB with 3.4-mW consumption at the nominal supply of 0.5 V, and occupies a die area of 0.9 mm(2).
著者He XY, Pun KP, Tang SK, Choy CS, Kinget P
期刊名稱Analog Integrated Circuits and Signal Processing
出版年份2011
月份2
日期1
卷號66
期次2
出版社Springer Verlag (Germany)
頁次255 - 267
國際標準期刊號0925-1030
電子國際標準期刊號1573-1979
語言英式英語
關鍵詞Analog-to-digital conversion; Continuous-time Delta-Sigma modulator; Low-voltage analog circuits
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

上次更新時間 2020-30-11 於 00:00