A 0.5V 2-1 Cascaded Continuous-Time Delta-Sigma Modulator Synthesized with a New Method
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員

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摘要This manuscript presents a new method of synthesizing cascaded continuous-time Delta-Sigma Modulators. The coefficients for each stage are obtained by a discrete-time to continuous-time transformation. A detailed derivation of the digital cancellation logics for modulators based on discrete-time domain analysis is presented which leads to a simple implementation of circuits and is capable of correcting the effect of RC value variation. The proposed synthesis method is applied to a 0.5-V 2-1 cascaded continuous-time Delta-Sigma modulator with switched-capacitor-resistor feedback. Transistor-level simulations show that a 98dB SNDR is achieved over a 25kHz signal bandwidth with a 6.4MHz sampling frequency and 350 mu W power consumption under a 0.5-V supply.
著者Chen Y, Pun KP
會議名稱53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)
會議開始日01.08.2010
會議完結日04.08.2010
會議地點Seattle
會議國家/地區美國
詳細描述organized by IEEE Circuits and Systems Society,
出版年份2010
月份1
日期1
出版社IEEE
頁次1165 - 1168
電子國際標準書號978-1-4244-7773-9
國際標準期刊號1548-3746
語言英式英語
Web of Science 學科類別Computer Science; Computer Science, Information Systems; Engineering; Engineering, Electrical & Electronic

上次更新時間 2020-25-11 於 00:16