A 0.5V 2-1 Cascaded Continuous-Time Delta-Sigma Modulator Synthesized with a New Method
Refereed conference paper presented and published in conference proceedings


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AbstractThis manuscript presents a new method of synthesizing cascaded continuous-time Delta-Sigma Modulators. The coefficients for each stage are obtained by a discrete-time to continuous-time transformation. A detailed derivation of the digital cancellation logics for modulators based on discrete-time domain analysis is presented which leads to a simple implementation of circuits and is capable of correcting the effect of RC value variation. The proposed synthesis method is applied to a 0.5-V 2-1 cascaded continuous-time Delta-Sigma modulator with switched-capacitor-resistor feedback. Transistor-level simulations show that a 98dB SNDR is achieved over a 25kHz signal bandwidth with a 6.4MHz sampling frequency and 350 mu W power consumption under a 0.5-V supply.
All Author(s) ListChen Y, Pun KP
Name of Conference53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)
Start Date of Conference01/08/2010
End Date of Conference04/08/2010
Place of ConferenceSeattle
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE Circuits and Systems Society,
Year2010
Month1
Day1
PublisherIEEE
Pages1165 - 1168
eISBN978-1-4244-7773-9
ISSN1548-3746
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Information Systems; Engineering; Engineering, Electrical & Electronic

Last updated on 2020-26-03 at 00:25