A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC
Publication in refereed journal

香港中文大學研究人員

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摘要A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-encient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-mu m CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73: 19 mu W under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.
著者Tang XA, Pun KP
會議名稱12th International Symposium on Integrated Circuits
會議開始日14.12.2009
會議完結日16.12.2009
會議地點Singapore
期刊名稱Journal of Circuits, Systems, and Computers
出版年份2011
月份2
日期1
卷號20
期次1
出版社World Scientific Publishing
頁次15 - 27
國際標準期刊號0218-1266
語言英式英語
關鍵詞current comparator; current steering DAC; S/H circuit; SAR ADC; switched-current
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

上次更新時間 2020-26-11 於 00:37