A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC
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AbstractA novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-encient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-mu m CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73: 19 mu W under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.
All Author(s) ListTang XA, Pun KP
Name of Conference12th International Symposium on Integrated Circuits
Start Date of Conference14/12/2009
End Date of Conference16/12/2009
Place of ConferenceSingapore
Journal nameJournal of Circuits, Systems, and Computers
Year2011
Month2
Day1
Volume Number20
Issue Number1
PublisherWorld Scientific Publishing
Pages15 - 27
ISSN0218-1266
LanguagesEnglish-United Kingdom
Keywordscurrent comparator; current steering DAC; S/H circuit; SAR ADC; switched-current
Web of Science Subject CategoriesComputer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC

Last updated on 2020-28-07 at 01:08