Go to Header
Go to Navigation
Go to Content
Go to Footer
Login
Help
中文（繁體）
Research Resources
CUHK UPDates
Theses
Experts List
User Guides
About Us
List of Researchers
> Jianping GUO
Home
Research Outputs
Researcher Profiles
Department Profiles
Research Areas
Dr GUO Jianping
(No longer affiliated with CUHK)
CUHK Research Outputs
A CMOS Low-Dropout Regulator With Dominant-Pole Substitution
(
2016
)
A Fast-Response Buck-Boost DC-DC Converter with Constructed Full-Wave Current Sensor
(
2016
)
A Regulated Voltage Multiplier for Passive RFID Tag
(
2016
)
A Shared-MSB Delay-Line-Based ADC with Simultaneous Quantization for Digital Control Single-Inductor-Multiple-Output DC-DC Converter
(
2016
)
A Single-Inductor Multiple-Output Auto-Buck-Boost DC-DC Converter With Autophase Allocation
(
2016
)
A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
(
2016
)
Digitally-assisted constant-on-time dynamic-biasing technique for bandwidth and slew-rate enhancement in ultra-low-power low-dropout regulator
(
2016
)
Regulated Voltage Multiplier for Passive RFID Tag
(
2016
)
A 0.7 V 24 μA Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW
(
2015
)
A 124-dB double-gain-boosted cascode amplifier with 92% rail-to-rail output swing
(
2015
)
A Digital-Control Sensorless Current-Mode Boost Converter with Non-Zero Error Bin Compensation and Seamless Mode Transition
(
2015
)
A Fixed-Frequency Auto-Buck-Boost SIMO DC-DC Converter with Duty-Cycle Redistribution and Duty-Predicted Current Control
(
2015
)
A robust cross-regulation-suppressed single-inductor multiple-output DC-DC converter with duty-regulated comparator control
(
2015
)
Gain and Slew Rate Enhancement for Amplifiers through Current Starving and Feeding
(
2015
)
Load regulation cancellation based on adaptive body bias for STC-LDOs
(
2015
)
Power-area-efficient transient-improved capacitor-free FVF-LDO with digital detecting technique
(
2015
)
Analysis of CMOS Low-Dropout Regulator - Power-Supply Rejection Ratio
(
2014
)
An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8 V
(
2014
)
A 25mA CMOS LDO with -85dB PSRR at 2.5MHz
(
2013
)
Share Link
Last updated on 2018-13-07 at 07:51
Share Link
Your name*
Your email*
Recipient's name*
Recipient's email*
Message
Auxilliary Information
No information will be stored or shared with any third party.
Cancel
Our policy towards the use of cookies
All Clarivate Analytics websites use cookies to improve your online experience. They were placed on your computer when you launched this website. You can change your cookie settings through your browser.
Ok to Continue
Cookie Policy
